On Connecting Cores to Packet Switched On-chip Networks: a Case Study with Microblaze Processor Cores

The idea of using on chip packet switched networks for interconnecting a large number of IP cores is very practical for designing complex SoCs since it gives possibility of not only reusing IP cores but also the interconnection infrastructure. However, the real effort and time in using these Networks on Chip (NoC) goes in developing interfaces for connecting cores to the on-chip network. Standardization of interfaces for these cores can speed up the development process. In this paper, we present our work of developing an interface for a standard bus called OPB to the on-chip network. Any cores having OPB as the wrapper can reuse this interface. The paper also describes implementation of a small NoC prototype using this idea on an FPGA platform. The performance measurements on the prototype not only demonstrate the feasibility of NoC implementation but also demonstrate that FPGA based NoC implementation will be able to meet the performance requirements in many application areas. Specifically, we show that a core can communicate 2.5 MPackets/sec to a neighboring core.